As semiconductor technologies evolve, three dimensional (3D) integrated circuits (ICs) emerge as an effective alternative to further reduce the physical size of a semiconductor chip. In a 3D IC based semiconductor chip, active circuits are fabricated on different wafers and each wafer die is stacked on top of another wafer die using pick-and-place techniques. Much higher density can be achieved by employing 3D IC. Furthermore, 3D ICs can achieve smaller form factors, cost-effectiveness, increased performance and lower power consumption.
During the development of 3D ICs, an intermediate stage called 2.5D ICs was created. In a 2.5D IC, there may be a variety of dies comprising active circuits and a plurality of interposers comprising through silicon vias (TSVs). Unlike a 3D IC, the variety of dies comprising active circuits in a 2.5D IC may not comprise TSVs. Instead, various 2.5D dies rely on a 2.5D interposer providing TSVs and further interconnecting the various 2.5D dies. Despite that 2.5D ICs may have a different structure from 3D ICs, 2.5D ICs are loosely considered as a subcategory of 3D ICs.
A 3D IC device may comprise a top active circuit layer, a bottom active circuit layer and a plurality of inter-layers. One of the inter-layers may be an interposer. In a 3D IC, both active circuit layers and interposers may comprise TSVs. As a result, a variety of active circuit layers may be stacked together in a 3D IC without an interposer. However, interposers in 3D ICs are still widely used because an interposer, as a relatively large silicon layer, can accommodate various wafer dies different in size. More particularly, interposers can bond various wafer dies together by using micro-bumps. Furthermore, by employing an interposer, the complicated thermal distribution issue of a 3D IC can be simplified.
TSVs are used to transfer signals between different layers of a 3D IC. Due to operation variations in a 3D IC fabrication process, defects may occur while forming TSVs before stacking different layers together. In order to ensure that the reliability and the yield of 3D ICs meet specifications, some key parameters of TSVs such as resistance, capacitance, leakage and the like are tested before stacking a variety of wafers together. The pre-stacking TSV testing can reduce yield losses due to defective TSVs.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.